lithographysystem

FEATURES

  • Upgraded CABL series as user-friendly multi user management.
  • Windows OS, conversion soft for GDSII & DXF CAD files.
  • Point beam.
  • TFE emitter.
  • Achieving <2nm line width with 50kV acceleration voltage.
  • High stitching & overlay accuracy.
  • Stable beam current & beam position.
  • Field size modulation (patented), minimum address size as 0.0012nm.
  • Chirped GRT.
  • Axial Symmetrical PatternWritting method.
  • Thermal cotroller.

APPLICATIONS

  • Ultra thin lines.
  • Line & space.
  • Dot patterns.
  • 3D processing.
  • Axial symmetrical patterns.
  • Si semiconductor.
  • Optical device.
  • MEMS devices.

SPECIFICATIONS

Gun/Acceleration Voltage TFE(ZrO/W) /5-50kV
Beam size/min. width 2.0nm/10nm
Scanning method Vector scan(X,Y), Vector scan(r,theta) standard
Raster scan,
spot scan(option)
Field size modulation,
Axial symmetrical pattern,
RAM DAC digital spot writing,
3D writing method.
Field size 30umx30um,60umx60um,
120umx120um,300umx300um,
600umx600um(standard)
1200umx1200um,2400umx2400um(option)
Pixel 20,000×20,000dot,60,000×60,000dot@vector
scan(estandar)240,000×240,000dot@vector
scan(opcion)4,000×4,000dot,
4,000×4,000dot,10,000×10,000dot
@raster scan(opcion).
Min. address size 10nm@600umx600um field,
2nm@120umx120um field(standard)|
0.0012nm@500umx500um field(standard)
Scan rate/Resolution Vector scan(Analog): 0.05-300uS/0.01us(standard)|
Vector scan(Digital): 0.2-300uS/0.1us(standard)|
Raster scan: 0.3-300uS/0.1us(Option)
Wafer size 4,6,8inchΦ(other size, other shape is OK)
Stitching accuracy 50nm(3sigma)@500umx500um,|
20nm(2sigma)@50umx50um
Overlay accuracy 50nm(3sigma)@500umx500um,|
20nm(2sigma)@50umx50um
CAD software original CAD(standard),
GDSⅡconversion(option),
DXF conversion(option)
OS Windows2000, XP